1. Field of the Disclosure
This disclosure relates to a liquid crystal display (LCD) device, and more particularly to an LCD device which prevents generation of a short-circuit between adjacent ones of the link lines formed in the same layer.
2. Description of the Related Art
LCD devices which recently receive attention as flat panel display devices exhibit a high contrast ratio, superior gradation or motion picture display, and low power consumption and are actively being developed. In particular, since the LCD device can be manufactured with a thin thickness, the LCD device may be used as an ultra-thin display device such as wall mount TVs. Also, due to its light weight and low power consumption characteristics, compared to cathode ray tubes (CRTs), the LCD device is used as displays for laptops operated by batteries and thus highlighted as one of the next generation display devices.
The LCD device includes a thin film transistor (TFT) array substrate where a TFT and a pixel electrode are formed in each pixel area defined by a gate line and a data line, a color filter substrate in which a color filter layer and a common electrode are formed, and a liquid crystal layer interposed between the TFT array substrate and the color filter substrate. Liquid crystal molecules in the liquid crystal layer are rearranged by applying a voltage to the electrodes. Thus, an image is displayed by controlling the quantity of light being transmitted.
Also, the LCD device can be manufactured into a compact panel and thus used in a variety of applied fields, for example, mobile phone displays.
FIG. 1 is a plan view of a general compact LCD device. FIG. 2 is a cross-sectional view showing the connection relationship between an auto probe pad and a gate link line. Referring to FIG. 1, a TFT array substrate 1 includes an active region 13 in which a plurality of pixel areas are defined by a plurality of gate lines G1, G2, G3, . . . , Gn-2, Gn-1, and Gn and a plurality of data lines D1, D2, D3, . . . , Dm-2, Dm-1, and Dm which cross each other, and an non-active region 14 connected by a gate pad and a data pad to a printed circuit board (not shown) that is an external driving circuit.
In detail, in the active region 13, the plurality of gate lines G1, G2, G3, . . . , Gn-2, Gn-1, and Gn and the plurality of data lines D1, D2, D3, . . . , Dm-2, Dm-1, and Dm are formed crossing each other. A TFT is formed as a switching device at a portion where each gate line and each data line cross each other. The TFT is connected to a pixel electrode with a protection layer interposed therebetween.
In the non-active region 14, a pad area 12 having a plurality of gate pad portions 15 for applying a gate driving signal to each of the gate lines G1, G2, G3, . . . , Gn-2, Gn-1, and Gn and a plurality of data pad portions 16 for applying a data signal to each of the data lines D1, D2, D3, . . . , Dm-2, Dm-1, and Dm is formed to interface an electric signal with an external driving circuit. For compact liquid crystal panels used for monitors of mobile phones, as shown in FIG. 1, the gate pad portions 15 and the data pad portions 16 are integrally arranged in a lower side of the liquid crystal panel in order to minimize the size of a pad portion area.
The gate pad portions 15 are formed at each end portion of a plurality of gate link lines LG1, LG2, LG3, . . . , LGn-2, LGn-1, and LGn, respectively, extending from the gate lines G1, G2, G3, . . . , Gn-2, Gn-1, and Gn. The data pad portions 16 are formed at each end portion of a plurality of data link lines LD1, LD2, LD3, . . . , LDm-2, LDm-1, and LDm, respectively, extending from the data lines D1, D2, D3, . . . , Dm-2, Dm-1, and Dm.
The gate link lines and the data link lines are arranged by being divided into an odd-numbered group and an even-numbered group. Any one of the groups is directly connected to the gate lines and the data lines. The other group are connected to the gate lines and the date lines via a contact hole formed in an insulation layer 22. As shown in FIG. 2, the gate link lines LG1, LG2, LG3, . . . , LGn-2, LGn-1, and LGn are divided into the two group of the odd-numbered gate link lines and the even-numbered gate link lines. Each link group is insulated by the gate insulation layer 22.
An auto probe pad 17 for testing driving of a liquid crystal panel is further provided in the pad area 12 and electrically connected to an auto probe (not shown) of a test equipment during the test of driving. The auto probe pad 17 is electrically connected each of the data link lines and the gate link lines. An electric signal applied from the test equipment during the test is applied to each of the data lines and the gate lines via the data link lines and the gate link lines so that the driving of a liquid crystal panel may be tested.
The auto probe pad 17 includes a plurality of pads which are arranged in parallel at a constant interval. As shown in FIG. 2, the first auto probe pad 25a that is any one of the pads is connected to the odd-numbered link line group while the second auto probe pad 25b is connected to the even-numbered link line group.
Since the link lines need to be formed in a narrow area, short-circuit (A in FIG. 2) is frequently generated between adjacent ones of the link lines formed in the same layer during the process of forming the link lines. Also, since an electric signal is equally applied to the first auto probe pad 25a, a short-circuit between the link lines generated in the odd-numbered gate link group connected to the first auto probe pad 25a may not be detected.